The present invention relates to a semiconductor integrated circuit for amplifying input signals.
FIG. 1 shows a differential amplifier that has been well known conventionally. This differential amplifier is a type of amplifier using a current mirror consisting of pMOS transistors TP1 and TP2 as a load. The differential amplifier receives input signals A and B from gate electrodes of nMOS transistors TN1 and TN2 respectively, amplifies a differential voltage of these input signals, and outputs the amplified signal from the node N between the pMOS transistor TP2 and the nMOS transistor TN2. A fixed bias voltage is applied to a gate electrode of an nMOS transistor TN3 as a constant current source.
This differential amplifier is also used as an input buffer. As shown in FIG. 2, the input buffer 4 is formed on a semiconductor ship 3 and the output buffer 2 is mounted on a separate semiconductor chip 1. The output buffer 2 outputs the signal A and the signal B that is the inverse signal of the signal A via the transmission paths 5 and 6 respectively. The input buffer 4 includes the differential amplifier shown in FIG. 1. The input buffer 4 supplies output signals to a main circuit formed within the same semiconductor chip 3. The signals A and B are applied to the gate electrodes of the MOS transistors TN1 and TN2 in the input buffer 4 respectively.
When the conventional differential amplifier is applied to the input buffer 4 shown in FIG. 2, a common level of an input signal that the input buffer 4 receives is different depending on the facing output buffer 2. The common level is a center level Vc between a maximum voltage VH0 and a minimum voltage VL0 of an amplitude of the input signal (Vc=(VH0+VL0)/2). When the common level becomes low for the input signal of the same amplitude, the voltage at the gate terminal versus the voltage at the source terminal of each of the MOS transistors TN1 and TN2 does not easily exceed the own threshold voltage. Therefore, the waveform of the output signal collapses, and the duty of the output signal versus the duty of the input signal changes, for example. Further, when the common level has lowered to an extent that the voltage at the gate terminal versus the voltage at the source terminal of each of the MOS transistors TN1 and TN2 does not completely exceed the own threshold voltage, the differential amplifier does not operate.
It is an object of the present invention to provide a semiconductor integrated circuit capable of outputting a signal of which level changes in response to an input signal even when the common level of the input signal has varied.
The semiconductor integrated circuit according to one aspect of the present invention comprises a first element for flowing a current from a voltage line applied with a first voltage to a first node, and a second element for flowing a current from the first node to a second voltage line applied with a second voltage, thereby to set a predetermined bias voltage.
The semiconductor integrated circuit is further provided with a first inverter having its output connected to the first node, for changing a voltage of the first node in a direction opposite to a direction of a voltage change of the input signal in response to the voltage change of the input signal, thereby to produce a voltage biased in a direction of a bias voltage having a common level of the input signal set to the first node.
The semiconductor integrated circuit is further provided with a second inverter having its output connected to the second node, for changing a voltage of the second node in a direction opposite to a direction of a voltage change of the first node in response to the voltage change of the first node, thereby to amplify a signal having an amplitude at the biased common level. With this arrangement, even when the common level of the input signal has varied, it is possible to output a signal of which signal level changes in response to the input signal.
According to another aspect of the invention, there is provided a semiconductor integrated circuit of the above aspect, wherein the first inverter has a third element connected between a third voltage line applied with the first voltage and the first node, for flowing a current from the third voltage line to the first node, and a fourth element connected between a fourth voltage line applied with the second voltage and the first node, for flowing a current from the first node to the fourth voltage line. In this case, when the first and second elements always flow currents and when the currents flown by the first and second elements are set larger than the currents flown by the third and fourth elements respectively, a variable range of the common level of the input signal becomes larger.
Further, according to still another aspect of the invention, there is provided a semiconductor integrated circuit of the above aspect, wherein the semiconductor integrated circuit further comprises a third inverter for changing a voltage of the second node in a direction opposite to a direction of a voltage change of a another input signal in response to the voltage change of the another input signal. When the another input signal is inversely logical to the input signal, the third inverter works to advance the voltage change of the first node.
The second inverter includes a MOS transistor having a drain terminal connected to the second node and a gate terminal connected to the node N1. The third inverter includes a MOS transistor having a drain terminal connected to the second node and a gate terminal for receiving the another input signal. When the driving capacity of the MOS transistor of the third inverter is smaller than that of the second inverter, a variable range of the common level of the input signal becomes larger.
According to still another aspect of the invention, there is provided a semiconductor integrated circuit of the above aspect, wherein the semiconductor integrated circuit further comprises a third element connected between a power source line for receiving a power source voltage and the first voltage line, for flowing a current from the power source line to the first voltage line. The first voltage line is connected in common to the first and second inverters. It is possible to reduce power consumption by adjusting the volume of current flowing through the third element. Similarly, the semiconductor integrated circuit further comprises a fourth element connected between a ground line for receiving a ground voltage and the second voltage line, for flowing a current from the second voltage line to the ground line. The second voltage line is connected in common to the first and second inverters. It is possible to reduce power consumption by adjusting the volume of current flowing through the fourth element.
The first inverter includes, for example, a p-channel type first transistor having a source terminal for receiving the first voltage, a drain terminal connected to the first node, and a gate terminal for receiving an input signal, and an n-channel type second transistor having a source terminal for receiving the second voltage, a drain terminal connected to the first node, and a gate terminal for receiving an input signal. Further, the second inverter includes for example, a p-channel type third MOS transistor having a source terminal for receiving the first voltage, a drain terminal connected to the second node, and a gate terminal connected to the first node, and an n-channel type fourth MOS transistor having a source terminal for receiving the second voltage, a drain terminal connected to the second node, and a gate terminal connected to the first node.
The third inverter includes, for example, a p-channel type fifth MOS transistor having a source terminal for receiving the first voltage, a drain terminal connected to the second node, and a gate terminal for receiving a another input signal, and an n-channel type sixth MOS transistor having a source terminal for receiving the second voltage, a drain terminal connected to the second node, and a gate terminal for receiving the another input signal.
As there are a small number of elements connected in series between the two voltage lines applied with the first and second voltage, it is possible to lower the voltage.
The first element includes a seventh MOS transistor connected between the first voltage line and the first node, and the second element includes an eighth MOS transistor connected between the first node and the second voltage line. The first and second MOS transistors have driving capacities smaller than those of the seventh and eighth MOS transistors respectively. When the third inverter has been provided, the fifth and sixth MOS transistors have driving capacities smaller than those of the third and fourth MOS transistors respectively. With this arrangement, a variable range of the common level of the input signal becomes larger.
In the mean time, when the driving capacities of the third and fourth MOS transistors are set the same as those of the seventh and eighth MOS transistors respectively, the second inverter amplifies large the voltage biased on the first node.
When the seventh and eighth MOS transistors are the p-channel type and n-channel type MOS transistors respectively, the number of the p-channel type MOS transistors becomes the same as the number of the n-channel type MOS transistors.
Preferably, in each of the seventh and eighth MOS transistors, the drain terminal is connected with the gate terminal.
According to still another aspect of the invention, the semiconductor integrated circuit comprises at least one of a third element connected between a power source line for receiving a power source voltage and the first voltage line, for flowing a current from the power source line to the first voltage line, and a fourth element connected between a ground line for receiving a ground voltage and the second voltage line, for flowing a current from the second voltage line to the ground line. The first voltage line is connected in common to at least the source terminals of the first and third MOS transistors. The second voltage line is connected in common to at least the source terminals of the second and fourth MOS transistors.
The first and second voltage lines may be connected to the source terminals of the fifth and sixth MOS transistors respectively.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.